This invention relates to programmable logic devices ("PLDs"), and more particularly to improved bit line sense amplifiers for PLDs.
Programmable logic devices ("PLDs") are well known as shown, for example, by such references as Hartmann et al. U.S. Pat. Nos. 4,617,479; Hartmann et al. 4,609,986; Veenstra 4,677,318; Hartmann et al. 4,713,792; Birkner et al. 4,124,899; Cavlan 4,703,206; and Spencer 3,566,153, all of which are hereby incorporated by reference herein. There is a continuing demand for PLDs which are both larger and faster. However, these two objectives conflict with one another because as the number of interconnected devices increases (in order to provide larger PLDs capable of performing more complex logic functions), circuit loading and propagation delay also tend to increase, thereby tending to decrease the switching sped of the PLD.
In view of the foregoing it is an object of this invention to provide improved circuits for PLDs which increase the switching speed of the PLD (e.g., by counteracting the effects of increased circuit loading).
It is a more particular object of this invention to provide improved bit line sense amplifier circuits for PLDs (e.g., bit line sense amplifier circuits which are capable of faster switching speeds).